In accordance with an example scenario, many cryptosystems are based on algorithms that perform modular reduction operations. Modular reduction operations may be expensive computationally, such as where they involve dividing two multi-precision numbers. Certain implementations of modular reduction operations may involve multi-precision division to be performed by a Central Processing Unit (CPU) or Arithmetic Logic Unit (ALU), which can consume a large number of clock cycles. A large number of clock cycles can result in reduced speed of cryptographic computations and increased power consumption. Since cryptosystems may be installed on devices with limited power (e.g., smart cards), optimizing modular reduction operations used in cryptographic computations may be beneficial.